Analog to digital converters (ADCs) are widely used in the many fields to convert an analog signal into a corresponding digital signal. The analog signal may be from any one of a wide variety of sources, such as wireless telephonic, other audio, video or data transmissions. Due in part to the generally higher flexibility and adaptability and lower cost associated with the hardware required for digital processing, digital processing of such analog signals is often desirable. Furthermore, digital storage is much more convenient than analogue storage. For these, as well as many other, reasons ADCs are of significant importance in the electronics and communications industry.
The accuracy and linearity of ADCs is of particular importance, and increasingly so when the taken in conjunction with modern trends to increase the proportion of signal processing which is carried out in the digital domain. A typical example is software defined radio (SDR), in which virtually all of the signal processing is carried out in the digital domain. For such applications, high sensitivity and highly linear ADCs are required, having a wide range.
For such reasons as well as others, it is important to be able to effectively calibrate the gain of an ADC in order to determine its linearity, and to correct for non-linearities if appropriate. Calibration may be carried out as part of the manufacturing and assembly of the device; however, alternative techniques such as background calibration are becoming increasingly common. These have the advantage that calibration may be carried out over the lifetime of the device, and do not require connection to expensive external calibration equipment, or the additional time required to connect to such equipment and carry out calibration as part of assembly and test.
An example of background gain calibration is disclosed in the paper. “Background into stage gain calibration technique for pipelines ADCs” by Keane, Hurst and Lewis, in IEEE transactions on circuits and systems—52(1) January 2005, p 32-43.
One method of gain calibration involves injecting a pseudo-random calibration signal into the amplifier, along with the amplifier input. An example of such a system is shown in FIG. 1. FIG. 1 shows a m-bit pipeline stage of an ADC, with gain calibration. In this example of an m-bit stage, m is an integer. The pipeline stage includes an ADC 1, which is connected to the input signal Vin. The ADC 1 converts the analog input signal Vin into an m-bit digital signal. The m-bit digital signal is input into a Digital to Analogue Converter (DAC) 2, which converts the digital signal back to a partial analog signal. The resulting partial analog signal is subtracted from the original input signal at adder 3. The residual signal, corresponding to the difference between the input analog signal and the partial analog signal is amplified in an amplifier 4 having a gain g. The amplified residual signal, Vout, is passed to the subsequent stage of the pipeline ADC. In a practical ADC pipeline stage, both the ADC and the DAC will introduce an error. In order to calibrate the stage, a known error is simulated and introduced into the ADC. The effect of this known error on the ADC and the adder is then determined, and the results used to calibrate the stage. The means used to generate the known error is random generator 5. The random generator 5 (or pseudo-random generator) generates a binary digital signal, with a value either +1 or −1.
The effect of including the signal from the random number generator on the transfer curve of the amplifier stage is shown in FIG. 2. For simplicity, an ideal stage is shown, wherein the transfer function is completely linear. The figure shows the stage output (Vout), on the y-axis for the range of inputs (Vin), and the x-axis. The figure is split into n+1 “sub-ranges”, from sub-range 0 on the far left of the figure to sub-range n on the far right of the figure, and which are explained in more detail herebelow; the figure is discontinuous in that not all of the ranges are shown, however, the centre two ranges, namely (n−1)/2, and (n+1)/2, are included. Two separate transfer functions, Tf1 and Tf2, are shown. Transfer function Tf1 corresponds to the transfer function including a +1 injected signal from the random generator 5; transfer function Tf2 corresponds to the transfer function including −1 injected from the random generator 5. A sub-range is a part of the full range of the input signal of the pipeline stage. ADC 1 selects the sub-range in which the input signal Vin is. The number of sub-ranges n+1 is determined by the resolution of the stage: for integer (m-bit) stage, n+1=2^m and for half-integer (m-0.5-bit) stage, n+1=(2^m)−1.
The multi-bit pipeline stage described above uses (2^m)−1 where “A” denotes “raised to the power of”, (i.e 2 to the power m, minus 1) capacitors and a set of switches in the DAC part. The frequency response of these capacitors and switches limits the maximum achievable working frequency of the complete converter. In order to increase the working frequency, an (m−0.5) bit stage is used (which can provide m effective bits) since only [(2^(m−1))−1] capacitors, and a set of switches are needed, which drastically reduces the number of interest interconnections required. That is to say, the reduction of the stage resolution by half a bit, from an integer (m) to a half-integer (m−0.5), reduces the number of capacitors required by a factor greater than two. For instance, a 2.5-bit stage contains 3 capacitors while a 3-bit stage uses 7 capacitors.
In such a half integer (m−0.5) bit stage, the gain calibration as described above is no longer possible.
United States patent application publication US2005/0275578 discloses a pipeline stage gain calibration incorporating a 2-state dither signal from a random number generator. Rather than being applied as a calibration signal, the dither signal is principally used to soften parasitic spurs in a signal spectrum, in other words it is generally frequency shaped, whilst calibration signals are not; however, in principle it would be possible to apply such a dither signal in calibration or test. Depending on which sub-range of the ADC is used, the two values which can be taken by the dither signal can differ: that is to say in the left-most sub-range, and the dither signal can take on the values of 0 or +Vref/4; in the right-most sub-range, the dither signal can take the values of −Vref/4 or 0; and in all other sub ranges the to the signal can take on the values of −Vref/4 or +Vref/4.
Although US2005/0275578 provides some improvement over the previous art as regards gain calibration of an ADC stage, there still remains an ongoing need for an alternative and improved gain calibration method, and in particular for such a method which allows for convenient and simple processing and for the gain extraction.